1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication, specifically to the formation of transistors.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (DRAM), typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection.
In order to increase efficiency of memory devices, there is an effort to create smaller memory cells. DRAM memory cells can shrink in several ways. One way to decrease the size of a memory cell is to reduce the minimum feature size (F). This generally occurs through new and advanced lithography and etching techniques. Memory cells can also be decreased by designing a smaller memory cell. For example many of the DRAM chips on the market today have a memory cell size of 8F2 or greater, where F is the dimension of the minimum feature for a given manufacturing process.
U.S. Pat. No. 6,734,482 issued to Tran, et al., describes the use of a bit line buried within an isolation trench. The memory cell described in that patent is a 6F2 memory cell. A conductive strap connects the bit line to the active area (source) of a planar transistor which does not use a vertical pillar. However, these designs can take up more chip real estate.
Vertical transistor designs can be used to decrease chip real estate occupied by a memory cell transistor. An example of a memory cell with a vertical transistor is disclosed in U.S. Pat. No. 6,756,625, issued to Brown, the disclosure of which is incorporate by reference herein. In that patent, the digit line is directly connected to a pillar used in the vertical transistor. However, this can be difficult to integrate into the process flow of a DRAM memory cell. Therefore, additional methods of forming vertical transistors are desirable.